While a referenced module instance looks similar to an IP on the block design canvas, there are some notable differences between an IP and a referenced module. An RTL module in the block design has an “RTL” marking on the component symbol as shown in the following figure.
You can also see some differences between packaged IP and referenced modules when viewing the source files in the Sources window. A module reference block shows up in a directory tree with an _wrapper extension, and not as an XCI file, as shown in the following figure.
When you reset the output products of a block design, the Vivado tools delete the source file, constraint files and other meta data associated with IP blocks; however, a module reference block just contains the source HDL; there is nothing to delete, as shown in the following figure.
In this figure, the IP within the project have been reset and there are no HDL under these IP. RTL modules have nothing to reset, so the HDL files show up under the RTL module even after resetting the output products.
Out-of-date IP are shown in the IP Status window, or reported by the appearance of a link in the block design canvas window, as shown in Editing the RTL Module After Instantiation. You can upgrade IP by clicking Upgrade Selected in the IP Status window.
Out-of-date reference modules are also reported by a link in the design canvas window, as shown in Editing the RTL Module After Instantiation. In addition you can force the refresh of a module using the Refresh Module command from the design canvas right-click menu.
While you cannot edit the RTL source files for a packaged IP, you can edit the RTL source for a module reference. Refer to HDL Parameters for Interface Inference for more information.
Because a referenced module is also not a packaged IP, you do not have control over the version of the module instance. The version of a referenced module as displayed in the IP view of the Block Properties window is controlled internally by the Vivado IP Integrator. If you want to have control over the vendor, library, name, and version (VLNV) for a block then you must package the IP as described in the Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118).
For the Module Reference feature there is also no parameter propagation across boundaries. You must use the attributes mentioned in Inferring Control Signals in a RTL Module to support design rule checks run by IP Integrator when validating the design. For example, IP Integrator provides design rule checks for validating the clock frequency between the source clock and the destination. By specifying the correct frequency in the RTL code, you can ensure that your design connectivity is correct.