The following is a list of all attributes supported by the IP packager, Module Reference flow, and their components.
- Attach to: Port
VLNV INTERFACE_NAME LOGICAL_NAME[,VLNV INTERFACE_NAME LOGICAL_NAME etc]
The first variant creates an interface according to the bus definition specified by
VLNV, with the name
INTERFACE_NAME and maps the port attached to the logical port
LOGICAL_NAME. Note that this needs to be specified for every port that must be part of the created interface, because the heuristic will not add any ports to this user created interface automatically. Through the addition of multiple triplets here, a port can be added to multiple interfaces, if desired.
The second variant only specifies the
the interface that this port will be a part of. Vivado takes care of
adding the individual ports, and inferring a name and the logical-to-physical mapping.
As an example, the code snippet in Figure 2 shows how ports
can be shown as being a part of the interface called
adder_input interface exists
in the IP catalog with all the ports correctly specified as shown in the following figure.
Given the pre-existing interface, attributes can be inserted in the VHDL source code below to make the ports of the module a part of the interface.
When the RTL code above is instantiated on the block design as a module reference block, the block design looks as follows.
- Attach to: Port
NAME VALUE [,NAME VALUE etc]
"XIL_INTERFACENAME" IFC_NAME,NAME VALUE [,NAME VALUE]
This sets Bus Interface parameter(s) as specified for all interfaces this port is part of. If the seconds variant is used, they are only be set for the names interface. Note that if it occurs, XIL_INTERFACENAME must be the first element in the list.
As an example let us assume that a reset port (
rst_n in the code snippet below) has a polarity of active-Low and we want to override this polarity to active-High for all the interfaces that this
rst_n port is a part of. This can be overridden as shown below. Note the setting on the attribute is called X_INTERFACE_PARAMETER.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity param_ff is generic( data_width : integer := 32); Port ( data_in : in STD_LOGIC_VECTOR ((data_width - 1) downto 0); clk : in STD_LOGIC; rst_n : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR ((data_width - 1) downto 0)); end param_ff; architecture Behavioral of param_ff is ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_PARAMETER : STRING; ATTRIBUTE X_INTERFACE_INFO of data_in: SIGNAL is "xilinx.com:user:ff_data_in:1.0 ff_data_in data_in"; ATTRIBUTE X_INTERFACE_PARAMETER of rst_n: SIGNAL is "POLARITY ACTIVE_HIGH"; begin process (rst_n, clk) begin if (rst_n = '0') then data_out <= (others => '0'); elsif (rising_edge(clk)) then data_out <= data_in; end if; end process; end Behavioral;
On the block design, the polarity of
rst_n, which is inferred as active-Low by default, now
changes to active-High (indicated by the bubble on the
- Attach to: Port
If set to
true, this port will not be automatically added to any interface inferred by the
In the following code snippet we have three input ports
c_in, but we do
not want to add the third port
c_in to the interface.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ignore_port is Port ( a_in : in STD_LOGIC; b_in : in STD_LOGIC; c_in : in STD_LOGIC; sum_out : out STD_LOGIC; carry_out : out STD_LOGIC); end ignore_port; architecture Behavioral of ignore_port is ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_IGNORE : STRING; ATTRIBUTE X_INTERFACE_INFO of a_in: SIGNAL is "xilinx.com:user:adder_input:1.0 adder_input a_in"; ATTRIBUTE X_INTERFACE_INFO of b_in: SIGNAL is "xilinx.com:user:adder_input:1.0 adder_input b_in"; ATTRIBUTE X_INTERFACE_IGNORE of c_in: SIGNAL is "true"; begin sum_out <= a_in OR b_in OR c_in; carry_out <= a_in XOR b_in XOR c_in; end Behavioral; When instantiated on the block design, this will be as shown below.
- Attach to: Port
MODE [MONITOR_MODE] [INTERFACE_NAME obsolete]
The last parameter is obsolete and ignored.
Sets the interface mode of all the interfaces that contain the port. Set only one MODE per interface; if there are more, they will be ignored altogether.
The following code snippet shows the usage.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity interface_mode is Port ( a_in : in STD_LOGIC; b_in : in STD_LOGIC; c_in : in STD_LOGIC; sum_out : out STD_LOGIC; carry_out : out STD_LOGIC); end interface_mode; architecture Behavioral of interface_mode is ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_MODE : STRING; ATTRIBUTE X_INTERFACE_INFO of a_in: SIGNAL is "xilinx.com:user:adder_input:1.0 adder_input a_in"; ATTRIBUTE X_INTERFACE_INFO of b_in: SIGNAL is "xilinx.com:user:adder_input:1.0 adder_input b_in"; ATTRIBUTE X_INTERFACE_INFO of c_in: SIGNAL is "xilinx.com:user:adder_input:1.0 adder_input c_in"; ATTRIBUTE X_INTERFACE_MODE of c_in: SIGNAL is "monitor"; begin sum_out <= a_in OR b_in OR c_in; carry_out <= a_in XOR b_in XOR c_in; end Behavioral;
The module reference module when instantiated on the block design, looks as follows. Note the magnifying glass icon on the cell to signify that the interface type if of “monitor”.
- Attach to: Component
VLNV [VLNV VLNV etc]
Specifies the priority order in which the heuristic tries to infer bus interfaces. The highest priority will be given to match the ports in the component first, in the order specified. This is the highest priority list and it overrides project settings, and repository order.