A bus interface is a grouping of signals that share a common function. An AXI4-Lite master, for example, contains a large number of individual signals plus multiple buses, which are all required to make a connection.
One of the important features of IP integrator is the ability to connect a logical group of bus interfaces from one IP to another, or from the IP to the boundary of the IP integrator design or even the FPGA I/O boundary. Without the signals being packaged as a bus interface, the symbol for the IP shows an extremely long and unusable list of low-level ports, which are difficult to connect one-by-one.
A list of signals can be grouped in IP-XACT using the concept of a bus interface with its constituent port map that maps the physical port (available on the RTL or the netlist of the IP) to a logical port as defined in the IP-XACT abstraction definition file for that interface type.
Xilinx® provides many interface definitions, including standardized AXI protocols and other industry standard signaling; however, some legacy or custom implementations have unique IP signaling protocols. You can define your own interface and capture the expected set of signals, and ensure that those signals exist between IP. For more information, see this link in Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118).