Using the ILA IP to Debug a Block Design - 2020.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
Release Date
2020.2 English
Important: Existing block designs can continue to use the Integrated Logic Analyzer (ILA) debug core. However, new block designs should use the System ILA debug core as described at Using the System ILA IP to Debug a Block Design.

If an ILA debug core is found in the block design, you will see the following INFO message:

[ 6] /ila_0: Xilinx recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.

You can instantiate an Integrated Logic Analyzer (ILA) in the IP integrator design, and connect nets that you are interested in probing to the ILA.

Use the following steps to instantiate an ILA:

  1. Right-click the block design canvas and select Add IP, as shown in the following figure.

  2. In the IP catalog, type ILA in the search field, select and double-click the ILA core to instantiate it on the IP integrator canvas.

    The following figure shows the ILA core instantiated on the IP integrator canvas.

  3. Double-click the ILA core to reconfigure it.

    The Re-Customize IP dialog box opens, as shown in the following figure.

    The default option under the General Options tab shows AXI as the Monitor Type.

    • If you are monitoring an entire AXI interface, keep the Monitor Type as AXI.
    • If you are monitoring non-AXI interface signals, change the Monitor Type to Native.

    You can change the Sample Data Depth and other fields as desired. For more information, see this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).

    You can only monitor one AXI interface using an ILA. Do not change the value of the Number of Slots. If you need to debug more than one AXI interface, then instantiate more ILA cores as needed.

    When you set the Monitor Type to Native, you can set the Number of Probes value, as shown in the following figure. Set this value to the number of signals you want to be monitored.

    The Number of Probes is set to 2 in the General Options tab. You can see under the Probe_Ports tab that two ports display. The width of these ports can be set to the desired value.

  4. Assuming that you want to monitor a 32-bit bus, set the Probe Width for Probe0 to 32.

    After you configure the ILA, the changes are reflected on the IP integrator canvas as shown in the following figure.

  5. After configuring the ILA, make the required connections to the pins of the ILA on the IP integrator canvas, as shown.

    If a pin connected to an I/O port is to be debugged, use MARK_DEBUG to mark the nets for debug. The following section describes this action.
  6. Follow on to synthesize, implement, and generate bitstream.

Often, the I/O ports of a block design need to be probed for debugging. If the I/O ports of interest are bundled into interface ports then you must take care when connecting these interface ports or pins to the ILA or VIO debug core. You must pull the signals of interest out of the bundled interface port or pin. For more information, see Connecting Interface Signals.

As an example, consider the MicroBlaze™ processor design for the KC705 board, shown in the following figure. This design has a GPIO configured to use both the 8-bit LED interface and the 4-bit dip switches on the KC705 board.

Figure 1. Monitoring Interface Signals in a Block Design

To monitor these I/O interfaces, do the following:

  1. Expand the GPIO interface pins so that you can see the individual signals that make up the interface pin.

    As you can see in the following figure, the GPIO interface consists of an 8-bit output pin (gpio_io_o[7:0), and the GPIO2 interface consists of a 4-bit input pin (gpio2_io_i[3:0]).

    To monitor these pins using debug probes you need to make them external to the block design. In other words, you must tie the pins inside the interface pin to an external port.

  2. Right-click the pin, and select Make External.

    You can see in the following figure that the pins that make up the GPIO and GPIO2 interface pins have been tied to external ports in the block design. Next, you must connect these pins to an ILA debug core.

    When you make the I/O pins of an interface external, by connecting the input or output pins to external ports, do not delete the connection between the top-level interface pin and the I/O port. As shown in the following figure, leave the existing top-level interface pin connected externally to the appropriate interface.

    When connecting to individual signals or buses of an interface, you will see a warning as shown below:

    WARNING: [BD 41-1306] The connection to interface pin /axi_gpio_0/gpio2_io_i is being overridden by the user. This pin will not be connected as a part of interface connection GPIO2.

    You must manually connect all of the pins of this individual signal or bus, as they will no longer be connected as part of the bundled interface.

    Important: This is an especially important concept when adding an ILA or VIO core to probe a signal. Often you will simply connect the ILA or VIO core to one pin of an interface, without realizing you have removed that signal from the bundled interface. The signal connection is broken unless you connect to other expanded interface pins as needed.
  3. Use the Add IP command to instantiate an ILA core into the design, and configure it to support either Native or AXI mode.
    Note: In this case you must configure the ILA to support Native mode because you are not monitoring an AXI interface.
  4. Configure two probes on the ILA core:
    • One that is 8-bits wide to monitor the LED
    • One that is 4-bits wide to monitor the DIP Switches
  5. Connect the ILA probes to the appropriate input/output pins, and connect the ILA clock to the same clock domain as that of the I/O pins, as shown in the following figure.

With the debug cores inserted into the block design, the generated output products will include the necessary logic and signal probes to debug the design in the Vivado hardware manager. For more information on working with the Vivado hardware manager, and programming and debugging devices, see this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).