Using the System ILA IP to Debug a Block Design - 2020.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

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2020.2 English
The System ILA debug core in IP integrator allows you to perform in-system debugging of block design on a Xilinx® device. This feature should be used when there is a need to monitor interfaces and signals in the design.

The IP integrator debugging flow has four distinct phases:

  1. Mark the interfaces or nets to be probed using the Debug option.
  2. Use Designer Assistance to connect the interfaces and nets to the System ILA core.
  3. Validate Design to ensure that design connectivity is correct.
  4. Implement the design, and debug the design on hardware using the Vivado Hardware Manager.

Nets can be marked for debug in the block design by right-clicking on the net and selecting Debug from the context menu as shown in the following figure.

Figure 1. Mark Nets to Debug from Context Menu

The nets that are marked for debug show a small bug icon placed on top of the net in the block design.

Figure 2. Bug Icons on Nets to be Debugged

Note that the Run Connection Automation link is active in the block design canvas banner.

Figure 3. Run Connection Automation to Connect Nets to be Debugged to System ILA

Clicking the Run Connection Automation link displays the Run Connection Automation dialog box, a provides the Run Connection Automation options shown in the following figure.

Figure 4. Selecting Data and/or Trigger Option for Interface Signals

Because the net being debugged in this case is an AXI Interface, interface pins such as Read/Write address and data pins are presented for setting Data and/or Trigger options. Similar options to set Data/Trigger options are presented when you mark a non-interface net is for debug and click the Run Connection Automation link.

Figure 5. Setting System ILA Options

As shown, the System ILA option provides the user with two separate options:

  • Auto: Lets the tool determine whether a new System ILA debug core should be used, or if the selected signals can be connected to an existing System ILA.
  • New: Specifically connects the selected debug signals to a new System ILA IP core. In some cases this may be desired to keep certain signals connected to a particular ILA.

When no System ILA are present in the block design, choosing either option will instantiate a new debug core. The clock domain of the net being debugged is determined by the tool and is connected to the clk pin of the System ILA IP. If nets to be debugged are in different clock domains, separate System ILA debug cores are instantiated as it can only be connected to one clock source.

The Run Connection Automation dialog box also provides you with the option to connect the interface to an AXI Memory Mapped Protocol Checker, as shown in the following figure. The AXI Protocol Checker monitors AXI interfaces. When attached to an interface, it actively checks for protocol violations and provides an indication of which violation occurred.

Tip: Additional details of debugging AXI interfaces in the Vivado Hardware Manager are described at this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).
Figure 6. Setting System ILA Options

When you click OK on the Run Connection Automation dialog box you see messages such as the following, indicating what action was taken by the tool:

Debug Automation : Instantiating new System ILA block '/system_ila_0' with mode INTERFACE, 1 slot interface pins and 0 probe pins. Also setting parameters on this block, corresponding to newly enabled interface pins and probe pins as specified via Debug Automation. 

Debug Automation : Connecting source clock pin /clk_wiz_1/clk_out1 to the following sink clock pins /system_ila/clk

Debug Automation : Connecting source reset pin /rst_clk_wiz_1_100M/peripheral_aresetn to the following sink reset pins :/system_ila_0/resetn

Debug Automation : Connecting interface connection /microblaze_0_axi_periph_M01_AXI, to System ILA slot interface pin /system_ila_0/SLOT_0_AXI for debug.

After a net has been marked for debug, you can remove the DEBUG attribute by right-clicking the net and selecting Clear Debug from the context menu, shown in the following figure. This automatically removes the connection of the selected net to the System ILA, and reconfigures the IP as needed for the appropriate number of Interfaces/Probes.

Figure 7. Removing Debug Cores from the Block Design