- In the Implementation
Complete dialog box, select Open Implemented Design and click OK to open the implemented design. When prompted to save the
project before opening an implemented design, click Don’t Save.
Now you are ready to set up and launch the Vivado simulator to run post implementation timing simulation. You will set the timing simulation properties in the Vivado IDE, then run the timing simulation.
- In the Flow Navigator, click Settings and select the Simulation to set the timing simulation properties. In the
box, note that the following defaults are automatically set:
- Simulation set: sim_1
- Simulation top-module name: testbench
- In the Elaboration tab, make sure that debug_level is set to typical, which is the default value.
- In the Simulation tab, set the SAIF file name xsim.simulate.saif to power_tutorial_timing_xsim.saif.
- Set the xsim.simulate.saif_scope to testbench/dut_fpga.
- Observe that the simulation run time xsim.simulate.runtime is 1000ns.
- Click OK.
With the simulation settings properly configured, you can launch the Vivado simulator to perform a timing simulation of the post implemented design.
- In the Flow Navigator, click
- After the Vivado simulator has
finished simulating the design, ensure that the SAIF file requested has been
generated. Check to see that the SAIF file requested in the simulation settings
prior to running simulation appears in this directory: