Define PM_CLK_RPU_PLL_OUT - 2021.1 English

Xilinx Standalone Library Documentation OS and Libraries Document Collection (UG643)

Document ID
UG643
Release Date
2021-06-16
Version
2021.1 English

Definition

#define PM_CLK_RPU_PLL_OUT(0x8208015U)

Description

Versal Clock Nodes