GPIO Device Used for Connecting PL Master JTAG Signals - 2021.1 English

Xilinx Standalone Library Documentation OS and Libraries Document Collection (UG643)

Document ID
UG643
Release Date
2021-06-16
Version
2021.1 English

In hardware design MASTER JTAG can be connected to any one of the available GPIO devices, based on the design the following parameter should be provided with corresponding device ID of selected GPIO device.

Master JTAG Signal Description
XSK_EFUSEPL_AXI_GPIO_DEVICE_ID Default = XPAR_AXI_GPIO_0_DEVICE_ID

This is for providing exact GPIO device ID, based on the design configuration this parameter can be modified to provide GPIO device ID which is used for connecting master jtag pins.