This function programs RSA enable secure control bits of eFUSE
Note: For ZynqMP silicon version 1.0 and 2.0 RSA authentication is enabled only by programming 24 and 25 bits of SEC_CTRL register but from silicon V3.0 bits 11:25 should be programmed
Prototype
INLINE u32 XilSKey_ZynqMp_EfusePs_Enable_Rsa(const u8 *SecBits_read);
Parameters
The following table lists the XilSKey_ZynqMp_EfusePs_Enable_Rsa
function arguments.
Type | Name | Description |
---|---|---|
const u8 * | SecBits_read | is a pointer which holds 32 bits of secure control register. |