Xil_DCacheInvalidateLine - 2021.1 English

Xilinx Standalone Library Documentation OS and Libraries Document Collection (UG643)

Document ID
UG643
Release Date
2021-06-16
Version
2021.1 English

Invalidate a Data cache line.

The cacheline is cleaned and invalidated.

Note: In Cortex-A53, functionality to simply invalid the cachelines is not present. Such operations are a problem for an environment that supports virtualisation. It would allow one OS to invalidate a line belonging to another OS. This could lead to the other OS crashing because of the loss of essential data. Hence, such operations are promoted to clean and invalidate which avoids such corruption.

Prototype

void Xil_DCacheInvalidateLine(INTPTR adr);

Parameters

The following table lists the Xil_DCacheInvalidateLine function arguments.

Table 1. Xil_DCacheInvalidateLine Arguments
Name Description
adr 64bit address of the data to be flushed.

Returns

None.