Flush a level 2 cache line.
If the byte specified by the address (adr) is cached by the L2 cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory before the line is invalidated.
void Xil_L2CacheFlushLine(u32 adr);
The following table lists the
Xil_L2CacheFlushLine function arguments.
|adr||32bit address of the data/instruction to be flushed.|