Xil_L2CacheInvalidateLine - 2021.1 English

Xilinx Standalone Library Documentation OS and Libraries Document Collection (UG643)

Document ID
UG643
Release Date
2021-06-16
Version
2021.1 English

Invalidate a level 2 cache line.

If the byte specified by the address (adr) is cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.

Note: The bottom 4 bits are set to 0, forced by architecture.

Prototype

void Xil_L2CacheInvalidateLine(u32 adr);

Parameters

The following table lists the Xil_L2CacheInvalidateLine function arguments.

Table 1. Xil_L2CacheInvalidateLine Arguments
Name Description
adr 32bit address of the data/instruction to be invalidated.

Returns

None.