Store a level 2 cache line.
If the byte specified by the address (adr) is cached by the L2 cache and the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory. After the store completes, the cacheline is marked as unmodified (not dirty).
void Xil_L2CacheStoreLine(u32 adr);
The following table lists the
Xil_L2CacheStoreLine function arguments.
|adr||32bit address of the data/instruction to be stored.|