This section describes how to provide input and capture the output from the
AI Engine array in hardware emulation using
AXI traffic generators. In the AI Engine
simulator the input data stimulus was provided using the simulation platform
construct.
PLIO("DataIn", adf::plio_32_bits, "data/input.txt")
For
hardware emulation an equivalent feature exists that emulates the behavior of this
PLIO and AXI4-Stream interface. Both Python and
C++ APIs are provided to make this easier to use.The primary external data interfaces for the AI Engine array are AXI4-Stream interfaces. These are known as PLIOs and allow the AI Engine to receive data, operate on the data, and send data back on a separate AXI4-Stream interface. The input interface to the AI Engine is an AXI4-Stream slave and the output is an AXI4-Stream master. To interact with these top level interfaces during hardware emulation complementary AXI4-Stream modules are provided. These complementary modules are referred to as the AXI traffic generators.
Note: The width of a PLIO
interface is an important system level design decision. The wider the interface the
more data can be sent per PL clock cycle.