Xilinx® provides a bare-metal software stack as part of the Vitis™ tools. The standalone software includes a simple, single-threaded environment that provides project domains such as standard input/output, and access to processor hardware features. The included board support packages (BSPs) and included libraries can be configured to provide the necessary functionality with the least overhead. You can locate the standalone drivers at the following path:
<Xilinx Installation Directory>\Vitis\<version>\data\embeddedsw\XilinxProcessorIPLib\driversYou can locate libraries in the following path:
<Xilinx Installation Directory>\Vitis\<version>\data\embeddedsw\lib\sw_servicesThe following figure illustrates the bare-metal software stack in the APU.
Figure 1. Bare-Metal Software Development Stack
Note: The software stack of libraries
and drivers layer for bare-metal in the RPU is same in the APU.
The bare-metal stack key components include:
- Software drivers for peripherals including core routines needed for using the Arm® Cortex®-A72, and the Cortex-R5F processors in the PS, and MicroBlaze™ processors in the PL.
- Bare-metal drivers for PS peripherals and optional PL peripherals.
- Standard C libraries: libc and libm, based on the open source Newlib library, ported to the Cortex-A72, Cortex-R5F, and the MicroBlaze processors.
- Embedded Libraries:
- LwIP 211
- Describes the SDK port of the third party networking library, Light Weight IP (lwIP) for embedded processors.
- XilFFS
- XilFFS is a generic FAT file system that is primarily added for use with SD/eMMC driver. The file system is open source and a glue layer is implemented to link it to the SD/eMMC driver.
- XilSecure
- Provides APIs to access secure hardware on the Zynq UltraScale+ MPSoCs.
- XilSkey
- Provides a programming mechanism for user-defined eFUSE bits and for programming the KEY into battery-backed RAM (BBRAM) of Zynq-7000 SoC, provides programming mechanisms for eFUSE bits of UltraScale devices.
- XilPM
- The Zynq UltraScale+ MPSoC and Versal ACAP power management framework is a set of power management options, based upon an implementation of the extensible energy management interface (EEMI).
- XilFPGA
- Provides an interface to the Linux or bare-metal users for configuring the PL over PCAP from PS. The library is designed for Zynq UltraScale+ MPSoC and Versal ACAP to run on top of Xilinx standalone BSPs.
- XilSEM
- The Xilinx Soft Error Mitigation (XilSEM) library is a pre-configured, pre-verified solution to detect and optionally correct soft errors in Configuration Memory of Versal ACAPs.
- Additional middleware libraries that provide networking, file system, and encryption support.
- Application examples include test applications.