PLM Boot and Configuration - 2021.1 English

Versal ACAP System Software Developers Guide (UG1304)
Document ID
UG1304
Release Date
2021-06-16
Version
2021.1 English

BootROM, PLM Handoff State

The BootROM loads the PLM into the PPU RAM from the boot device and is responsible for releasing the PPU from reset to start the PLM execution..

The PLM ELF is loaded to the PPU RAM. The PMC RAM is used to load the PMC DATA CDO file.

The state of the system at BootROM handoff is as follows:

  • The PPU is sleeping with the reset released, in case of normal JTAG boot mode (when PDI is not loaded in JTAG mode. This is the Zynq UltraScale+ MPSoC equivalent).
  • The PPU RAM and PMC RAM are initialized with error code correction (ECC).
  • The JTAG IDCODE instruction is always available regardless of the boot mode. Except the JTAG IDCODE instruction, all other JTAG instructions can be disabled when you program the required eFUSEs. If the eFUSEs are not programmed and a secure boot occurs, then only the base JTAG instructions are supported. When the AUTH_JTAG enable instruction is sent to the Versal ACAP in a secure boot mode, the full set of JTAG instructions (base +extended) can be enabled.
  • The boot device is taken out of reset and initialized.

PLM Subsystem

PLM and PMC CDO together constitute the PLM subsystem. PMC CDO contains the details of the device topology, subsystem details, and PMC configuration data.

Table 1. Components of the PLM Subsystem
File Contents
PLM ELF PLM ELF File
PMC CDO PMC CDO file
  • Device topology subsystem details
  • PMC Configuration: Register writes/polls for MIO, clocks, resets

The BootROM loads the PLM ELF and PMC CDO files to the PPU RAM and PMC RAM, respectively.

After the BootROM handoff to the PLM, the PLM performs the following tasks:

  • Initializes the PPU and register interrupts.
  • Initializes the modules to register the CDO/IPI commands and handlers.
  • Configures the PMC CDO file.
    • Device topology with PMC CDO commands to registers the nodes.
    • General/platform management calls to initialize the PMC and LPD MIO, clocks, etc.
      • PMC initialization for clocks, MIOs, resets.

LPD Configuration

LPD configuration contains configuration data that is required to initialize the LPD peripherals and clocks.

Table 2. LPD Configuration
File Contents
LPD CDO
  • PS LPD PM init node commands (SC, LBIST, BISR, MBIST)
  • LPD configuration: Register writes/polls
PSM ELF PSM ELF file

After initializing the PMC CDO:

  • The PLM re-initializes the boot device and loads the LPD CDO file from the boot device.
    • Configures the LPD CDO file.
    • Initiates the Scan Clear, BISRs, MBIST as required for LPD.
    • XilPM releases resets and powers up the nodes based on the CDO requirements.
  • The PLM loads the PSM ELF file and waits until initialization is complete.

Before loading the LPD configuration, ensure that PMC.CDO is configured.

PL Configuration

In Versal ACAP, the Adaptable Engine (PL) consists of CDO and NPI files. CDO mainly contains Cframe data along with PL and NoC power domain initialization commands. NPI contains configuration data related to the NPI blocks. NPI blocks include NoC elements (NMU, NSU, NPS, NCRB), DDR memory, XPHY, XPIO, GTY, MMCMs, etc.).

The NPI data is generated by the Vivado tool for the various NPI blocks. The NPI blocks that are present in Versal ACAP include NoC, DDR memory controller, XPHY, XPIO, GTY, MMCMs, etc. Before loading the PL configuration, ensure that PMC is configured.

The following table describes the content of the files, and is useful for debugging

Table 3. PL Configuration
File Contents
PL CDO <.rcdo>
  • PM init node command (Scan Clear, BISR, MBIST)  for NoC domain
  • The PM init node commands for scan clear, house cleaning, BISR of PL domain
  • Register writes to configure CFU for CRC, compression etc
  • DMA Keyhole Xfer commands to load CFI data
  • Register writes/polls to CFU
  • If NPI not present:
    • Global Signals (GMC_B, GRESTORE, GHIGH_B..): Register writes/polls
  • Global Signals (GWE, EOS, EN_GLOb): Register writes/polls
NPI CDO <.rnpi> NPI data
  • NPI data load: DMA Writes/register writes
  • If CFI present:
    • Global Signals (GMC_B, GRESTORE, GHIGH_B..:) Register writes/polls
  • NPI Sequence: Register writes/polls
  • If CFI present:
    • Global Signals (GWE, EOS, EN_GLOb): Register writes/polls
  • Isolation and PL reset commands

FPD Configuration

FPD CDO contains FPD configuration data with PM FPD initialization commands and FPD peripheral initialization data.
Note: PSM ELF dependency is already provided with LPD.
Table 4. FPD Configuration
File Contents
FPD CDO
  • PS FPD PM init node commands (SC, BISR, MBIST)
  • FPD configuration: Register writes/polls

Before loading the FPD CDO, ensure that the PMC and LPD are configured.

DFX Configuration

Dynamic Function eXchange (DFX) configuration enables one or more sub-regions of the device to be independently reprogrammed with new configuration data while all remaining regions (static or reconfigurable) remain active and unaffected. The DFX PDI can come either from PCIe, DDR memory, or the primary boot device. For loading the DFX PDIs, the XilLoader CDO commands can be used using the IPI interface. XilFPGA provides the required APIs to load DFx PDIs from Cortex-A72 or Cortex-R5F.

CPM Configuration

  • CPM: CPM configuration CDO with register writes

Before loading the CPM CDO, ensure that the PMC, LPD and stage1 PL configuration are completed. Stage1 PL configuration should contain XPIPE, GT, and NoC configuration data in the NPI file.

Processor Subsystem Configuration

The APU and RPU come under the processor- based subsystems. For all processor-based subsystems, ELF files and/or CDOs are present as a part of the image. Processor details are read from image headers and the processor is initialized using XilPM commands.

The configuration consists of the following files.

Table 5. Processor Subsystem Configuration
File Contents
PSM/RPU/APU CDO files
  • (Optional) Set of PM commands with nodes and requirements
PSM/RPU/APU ELF files
  • Cortex-R5F processor applications: Bare- metal/RTOS
  • Cortex-A72 processor applications: ATF/U-Boot/Linux/Bare-metal
  • For loading Cortex-R5F processor applications, ensure that the LPD configuration is completed.
  • For loading Cortex-A72 processor applications, ensure that the FPD configuration is completed.
  • For loading Cortex-R5F/Cortex-A72 using DDR memory, ensure that the PL (NPI with DDR configuration) configuration is completed.
  • For loading Cortex-R5F/Cortex-A72 processor applications to the DDR memory, enable the NoC path from the PMC to the DDR memory in the design.

AI Engine Configuration

The AI Engine configuration consists of the following files.

Table 6. AI Engine Configuration
File Contents
AI Engine NPI CDO AI Engine Global Configuration using NPI
  • PLL configuration
  • AI Engine scan clear and memory clear using PM initialization node commands
AI Engine ELF AI Engine tile program and data memory
AI Engine CDO AI Engine array configuration
  • Program memory configuration
  • Data memory configuration
  • DMA, locks, stream switch configuration
  • AI Engine module register configuration

Before loading the AI Engine NPI CDO, ensure that PLM, LPD and PL (with NoC configuration in the NPI file) are completed. Also, enable the NoC path from the PMC to the AI Engine in the design for PLM to clear the AI Engine data memories.