IBUF - 2021.1 English

Versal Architecture Prime Series Libraries Guide (UG1344)

Document ID
UG1344
Release Date
2021-06-16
Version
2021.1 English

Primitive: Input Buffer

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: INPUT_BUFFER

Introduction

Single-ended signals used as simple inputs must use an input buffer (IBUF).

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port Direction Width Function
I Input 1 Buffer input connected to a top-level input port.
O Output 1 Buffer output connected to internal device circuitry.

Design Entry Method

Instantiation Yes
Inference Recommended
IP and IP Integrator Catalog No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IBUF: Input Buffer
--       Versal Prime series
-- Xilinx HDL Language Template, version 2021.1

IBUF_inst : IBUF
port map (
   O => O, -- 1-bit output: Buffer output
   I => I  -- 1-bit input: Buffer input
);

-- End of IBUF_inst instantiation

Verilog Instantiation Template


// IBUF: Input Buffer
//       Versal Prime series
// Xilinx HDL Language Template, version 2021.1

IBUF IBUF_inst (
   .O(O), // 1-bit output: Buffer output
   .I(I)  // 1-bit input: Buffer input
);

// End of IBUF_inst instantiation

Related Information

  • Versal ACAP SelectIO Resources Architecture Manual (AM010)