Primitive: Bidirectional Buffer with Input Path Disable and On-die Input Termination Disable
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: BIDIR_BUFFER
The IOBUF_INTERMDISABLE primitive is available in the HD I/O banks. It has an IBUFDISABLE port that can be used to disable the input buffer during periods that the buffer is not being used. The IOBUF_INTERMDISABLE primitive also has an INTERMDISABLE port that can be used to manually disable the optional on-die receiver termination feature.
The IOBUF_INTERMDISABLE primitive can disable the input buffer and force the O output to the internal logic to a logic-Low when the IBUFDISABLE signal is asserted High and the output buffer is 3-stated (T = High). If the I/O is using the on-die receiver termination feature (uncalibrated), this primitive disables the termination legs whenever the INTERMDISABLE signal is asserted High and the output buffer is 3-stated (T = High). When the output buffer is 3-stated (T = High), the input buffer and any on-die receiver termination are controlled by IBUFDISABLE and INTERMDISABLE, respectively. The USE_IBUFDISABLE attribute must be set to TRUE and the SIM_DEVICE set to the appropriate value for this primitive to have the expected behavior that is specific to the architecture. When the output buffer is not 3-stated (T = Low), the input buffer and any on-die receiver termination are disabled and the O output (to the internal logic) is forced to a logic-Low. These features can be combined to reduce power whenever the input is idle for a period of time.
I/O attributes that do not impact the logic function of the component, such as IOSTANDARD and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).
|I||Input||1||Buffer input representing the output path from the device.|
|IBUFDISABLE||Input||1||Disables input path through the buffer and forces to a logic Low. This feature is generally used to reduce power at times when the I/O is idle for a period of time.|
|INTERMDISABLE||Input||1||Control to enable/disable on-chip input termination. This is generally used to reduce power in long periods of an idle state.|
|IO||Inout||1||Bidirectional I/O port connection. Connect directly to top-level port in the design.|
|O||Output||1||Buffer output representing the input path to the device.|
|T||Input||1||3-state enable input signifying whether the buffer acts as an input or output.|
Design Entry Method
|IP and IP Integrator Catalog||No|
|SIM_DEVICE||STRING||"VERSAL_PRIME", "VERSAL_PRIME_ES1", "VERSAL_PRIME_ES2"||"7SERIES"||Set the device version for simulation functionality.|
|USE_IBUFDISABLE||STRING||"TRUE", "FALSE"||"TRUE"||Set this attribute to "TRUE" to enable the IBUFDISABLE pin.|
VHDL Instantiation Template
Library UNISIM; use UNISIM.vcomponents.all;
-- IOBUF_DCIEN: Input/Output Buffer DCI Enable -- Versal Prime series -- Xilinx HDL Language Template, version 2021.1 IOBUF_DCIEN_inst : IOBUF_DCIEN generic map ( SIM_DEVICE => "VERSAL_PRIME", -- Set the device version for simulation functionality (VERSAL_PRIME, -- VERSAL_PRIME_ES1) USE_IBUFDISABLE => "TRUE" -- Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL) ) port map ( O => O, -- 1-bit output: Buffer output DCITERMDISABLE => DCITERMDISABLE, -- 1-bit input: DCI Termination Disable I => I, -- 1-bit input: Buffer input IBUFDISABLE => IBUFDISABLE, -- 1-bit input: Buffer disable input, high=disable IO => IO, -- 1-bit inout: Buffer inout (connect directly to top-level port) T => T -- 1-bit input: 3-state enable input ); -- End of IOBUF_DCIEN_inst instantiation
Verilog Instantiation Template
// IOBUF_DCIEN: Input/Output Buffer DCI Enable // Versal Prime series // Xilinx HDL Language Template, version 2021.1 IOBUF_DCIEN #( .SIM_DEVICE("VERSAL_PRIME"), // Set the device version for simulation functionality (VERSAL_PRIME, // VERSAL_PRIME_ES1) .USE_IBUFDISABLE("TRUE") // Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL) ) IOBUF_DCIEN_inst ( .O(O), // 1-bit output: Buffer output .DCITERMDISABLE(DCITERMDISABLE), // 1-bit input: DCI Termination Disable .I(I), // 1-bit input: Buffer input .IBUFDISABLE(IBUFDISABLE), // 1-bit input: Buffer disable input, high=disable .IO(IO), // 1-bit inout: Buffer inout (connect directly to top-level port) .T(T) // 1-bit input: 3-state enable input ); // End of IOBUF_DCIEN_inst instantiation
- Versal ACAP SelectIO Resources Architecture Manual (AM010)