Adding False Path Constraints - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2021-07-26
Version
2021.1 English

False path exceptions can be added to timing paths to ignore slack computation on these paths. It is usually difficult to prove that a path does not need timing to be functional, even with simulation tools. Xilinx does not usually recommend using a false path unless the risk associated with it has been properly assessed and appear to be acceptable.