Browse the Board Schematics - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
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2021.1 English

For a group of I/O ports connected to another device interface on the board, you can use the board clock that is connected to both the Xilinx device and to the external device interface as the reference clock for the input or output delay constraints. To control the timing of the related group of ports, you must verify in the external device data sheet that the board clock is internally transformed for timing the I/O ports, which ensures that the design generates the same clock inside the Xilinx device.