Common Mistakes - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
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2021.1 English

Following are common mistakes that you must avoid:

  • Relaxing setup without adjusting hold back to same launch and capture edges in the case of a multicycle path not functionally active at every clock cycle.

    The hold requirement can become very high (at least one clock period in most cases) and impossible to meet.

  • Setting a multicycle path exception between incorrect points in the design.

    This occurs when you assume that there is only one path from a startpoint cell to an endpoint cell. In some cases, this is not true. The endpoint cell can have multiple data input pins, including clock enable and reset pins, which are active on at least two consecutive clock edges.

    For this reason, Xilinx recommends that you specify the endpoint pin instead of just the cell (or clock). For example, the endpoint cell REGB has three input pins: C, EN and D. Only the REGB/D pin should be constrained by the multicycle path exception, not the EN pin because it can change at every clock cycle. If the constraint is attached to a cell instead of a pin, all the valid endpoint pins are considered for the constraints, including the EN (clock enable) pin.

    To be safe, Xilinx recommends that you always use the following syntax:
    set_multicycle_path -from [get_pins REGA/C] \
    -to [get_pins REGB/D] -setup 3
    set_multicycle_path -from [get_pins REGA/C] \
    -to [get_pins REGB/D] -hold 2