Platforms target any application implemented in hardware using the Vitis tools. The hardware components of a platform are designed using the Vivado IP integrator. The software components of a platform are created using the Vitis or PetaLinux tool chain.
This section describes the flow used to create and configure hardware components of a platform using the IP integrator. A design created using the IP integrator captures the logical and physical interfaces to the hardware functions from the Vitis environment. The processors, memory, and all external board interfaces are configured using a combination of Xilinx IP, custom IP, and RTL. This provides a logical wrapper for the hardware functions to be executed properly on the platform. There are multiple configuration and customization options for the types of hardware functions being accelerated.
An extensible platform is the foundation of the platform-based design flow. For example, a platform can enable the Vitis tools to add AI Engine and PL kernels. A platform can also allow kernels to access memory, interrupt controllers, resets, and clocking resources.
Following are the steps to build a platform in IP integrator:
- Instantiate the necessary IP to create the hardware portion of the
This might include properly configuring the CIPS, NoC, Processor System Reset Module, and Clocking Wizard IP to meet the needs of the intended platform. The input and output pins of these blocks are used by the hardware functions. Hardware functions are built by the Vitis tools at a later step.
- After building a block design in the IP integrator, declare and add platform
(PFM) interfaces and properties on the IP blocks before exporting the design as a
hardware platform to the Vitis environment.
These platform settings include clocking, interrupts, resets, memory, and processor AXI interfaces required for hardware functions within the Vitis environment. The IP integrator GUI provides a Platform Setup window to declare these interfaces along with their properties.
Following are requirements for the PFM step:
- There must be at least one enabled AXI port master interface within the platform.
- A platform can have one or more clocks. There must be at least one enabled clock interface within the platform. If a hardware function uses a particular clock, then it uses the synchronized reset output for that clock.
- Interrupts are typically connected in the platform via the Concat block.
- Export the hardware definition (XSA) to the Vitis
environment after generating the design.
This exports the necessary XML files needed for the Vitis tools to interpret the IP used in the design and also exports the memory mapping from the processor perspective.
The Vitis tools create a final block design containing the hardware functions (packaged as HLS IP) instantiated in the block design. All the necessary connections to clocks, resets, interrupts, and any AXI SmartConnect IP are connected appropriately by the Vitis tools build scripts.
For more information on IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).