Deciding When to Instantiate or Infer - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2021.1 English

Xilinx recommends that you have an RTL description of your design; and that you let the synthesis tool do the mapping of the code into the resources available in the device. In addition to making the code more portable, all inferred logic is visible to the synthesis tool, allowing the tool to perform optimizations between functions. These optimizations include logic replications; restructuring and merging; and retiming to balance logic delay between registers.