The Vivado IDE times the paths between all the clocks in your design by default. You can use the following constraints to modify this default behavior:
- Disables timing analysis between groups of clocks that you identify but not between the clocks within a same group.
- Disables timing analysis between the clocks only in the direction specified by
In some cases, you might want to use the following constraints on one or more paths of the clock domain crossing (CDC) to limit latency or bus skew:
- Sets the maximum delay constraints on asynchronous CDC paths to limit the latency.
Note: If clock groups or false path constraints already exist between the clocks or on the same CDC paths, the maximum delay constraints will be ignored. Therefore, it is important to thoroughly review every path between all clock pairs before choosing one CDC timing constraint over another to avoid constraints collision.Recommended: Xilinx also recommends running
report_methodologyto identify when a
set_max_delay -datapath_onlyconstraint is overridden by a
- Constrains a set of signals between asynchronous CDC paths by bus skew instead of latency.
Tip: You can also set a bus skew constraint from the Vivado IDE. In the Timing Constraints window, expand Assertions, and double-click Set Bus Skew.