It is important to plan properly for all Versal™ ACAP designs. Versal devices have several unique IP, which have significant implications on how you map your design to the Versal architecture and which design flow you choose to build your design. When creating a traditional design or Vitis™ platform, the Control, Interface, and Processing System (CIPS) IP must be incorporated into your design to boot the system on a chip (SoC). In addition, when creating a Vitis platform, you must decide which portion of your design resides in the platform, plan how data moves through your design, and choose which platform interfaces are accessible from the user portion of your design. Finally, if you plan to use Dynamic Function eXchange (DFX) in your design, you must pay careful attention to the boundary nets and the floorplan. Time invested in planning your design up-front helps to maximize your use of the Versal architecture.