To enable GT sharing, Xilinx IP that uses GT components does not integrate the GT components in the IP. Instead, the Xilinx IP is added standalone in the Vivado IP integrator, and block automation is used to connect TX and RX data paths of the IP to the GT Wizard. A new GT Wizard Quad base is launched if it cannot pack the parent IP with existing GT Quad resources. It also uses optional usrclk, outclk, REFCLK, and reset connections. For an overview of creating a design with GT parent IP, see this link in the Versal ACAP Transceivers Wizard LogiCORE IP Product Guide (PG331). For information on the block automation options, see the respective Xilinx IP product guides.