The GSR net initializes all registers to the specified initial value in the HDL code. If no initial value is supplied, the synthesis tool is at liberty to assign the initial state to either zero or one. Vivado synthesis generally defaults to zero with a few exceptions such as one-hot state machine encodings.
Any inferred SRL, memory, or other synchronous element may also have an initial state defined that will be programmed into the associated element upon configuration.
Xilinx highly recommends that you initialize all synchronous elements accordingly. Initialization of registers is completely inferable by all major device synthesis tools. This lessens the need to add a reset for the sole purpose of initialization, and makes the RTL code more closely match the implemented design in functional simulation, as all synchronous element start with a known value in the device after configuration.
Initial state of the registers and latches VHDL coding example one:
signal reg1 : std_logic := '0'; -- specifying register1 to start as a zero signal reg2 : std_logic := ‘1’; -- specifying register2 to start as a one signal reg3 : std_logic_vector(3 downto 0):="1011"; -- specifying INIT value for 4-bit register
Initial state of the registers and latches Verilog coding example two:
reg register1 = 1’b0; // specifying regsiter1 to start as a zero reg register2 = 1’b1; // specifying register2 to start as a one reg [3:0] register3 = 4’b1011; //specifying INIT value for 4-bit register
Another possibility in Verilog is to use an
reg [3:0] register3; initial begin register3= 4’b1011; end