Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All Versal™ ACAP design process Design Hubs can be found on the Xilinx.com website. This document covers the following design processes:
- Hardware, IP, and Platform Development
- Creating the PL IP blocks for the hardware platform, creating PL kernels, functional simulation, and evaluating the Vivado® timing, resource use, and power closure. Also involves developing the hardware platform for system integration.
For additional methodology information, see the following documents:
- System and Solution Planning
- Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine. See the Versal ACAP Design Guide (UG1273) and Versal ACAP System and Solution Planning Methodology Guide (UG1504).
- Embedded Software Development
- Creating the software platform from the hardware platform and developing the application code using the embedded CPU. Also covers XRT and Graph APIs. See the Programming the PS Host Application in the AI Engine Documentation flow of the Vitis Unified Software Platform Documentation (UG1416).
- AI Engine Development
- Creating the AI Engine graph and kernels, library use, simulation debugging and profiling, and algorithm development. Also includes the integration of the PL and AI Engine kernels. See the Versal ACAP AI Engine Programming Environment User Guide (UG1076) and AI Engine Kernel Coding Best Practices Guide (UG1079).
- System Integration and Validation
- Integrating and validating the system functional performance, including timing, resource use, and power closure. See the Versal ACAP System Integration and Validation Methodology Guide (UG1388).
- Board System Design
- Designing a PCB through schematics and board layout. Also involves power, thermal, and signal integrity considerations. See the Versal ACAP Board System Design Methodology Guide (UG1506).