Topologies with and without Placement Rules - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2021-07-26
Version
2021.1 English
Constrained Source Unconstrained Destination Behavior
GCIO BUFGCE/MBUFGCE, BUFGCTRL/MBUFGCTRL, BUFGCE_DIV/MBUFGCE_DIV, MMCM/XPLL/DPLL Automatically placed in same clock region
MMCM/XPLL/DPLL BUFGCE/MBUFGCE, BUFGCTRL/MBUFGCTRL, BUFGCE_DIV/MBUFGCE_DIV Automatically placed in same clock region
GT*_QUAD BUFG_GT/MBUFG_GT Automatically placed in same clock region
BUFGCTRL BUFGCTRL

Automatically placed in same clock region

Note: You can override placement within same clock region by using the CLOCK_REGION constraint.
BUFG*/MBUFG* BUFG*/MBUFG*

Unpredictable placement of unconstrained destination BUFG*/MBUFG*

Recommend constraining destination BUFG*/MBUFG* using the CLOCK_REGION constraint

Note: This excludes BUFGCTRL -> BUFGCTRL.
BUFG*/MBUFG* MMCM/XPLL/DPLL

Unpredictable placement of unconstrained destination MMCM/XPLL/DPLL

Recommend constraining MMCM/XPLL/DPLL using a LOC constraint

Recommend CLOCK_DEDICATED_ROUTE constraint when the route spans adjacent or multiple clock regions