A primary clock (that is, an incoming board clock) should be used when it directly controls the I/O path sequential cells, without traversing any clock modifying block. I/O delay lines are not considered as clock modifying blocks because they only affect the clock insertion delay and not the waveform. This case is illustrated by the two examples provided in Defining Input Delays and Defining Output Delays. Most of the time, the external device also has its interface characteristics defined with respect to the same board clock.
When the primary clock is compensated by an HDIO DPLL inside the device with the zero hold violation (ZHOLD) mode, the I/O paths sequential cells are connected to a phase detector deskewed internal copy (for example, a generated clock) of the primary clock. Because the waveforms of both clocks are identical, Xilinx recommends using the primary clock as the reference clock for the input/output delay constraints.
The constraints are identical to the example provided in Defining Input Delays because the HDIO ZHOLD DPLL acts like a clock buffer with a negative insertion delay, which corresponds to the amount of compensation.