Consider the following when performing debug and verification with Vitis HLS:
- Ensure the C++ source code is properly verified and fully functional before compiling it with Vitis HLS. In most cases, you can use standard C++ verification methods and your preferred C++ compiler and IDE.
- After you create a test bench for your C++ code, Xilinx recommends importing the test bench into your Vitis HLS project to leverage the verification features built into the flow.
- Prior to synthesizing the design with Vitis HLS, use the pre-synthesis C simulation flow to verify that your design works correctly in the Vitis HLS environment. For more information, see Verifying Code with C Simulation in the Vitis HLS flow of the Vitis Unified Software Platform Documentation (UG1416)).
- After synthesizing the design, use the post-synthesis C/RTL co-simulation flow to verify that the generated RTL behaves as expected. Running the C/RTL co-simulation flow also generates profiling information useful for analyzing the performance of the design.
- Use Vitis hardware emulation to test the integration of the kernel with the software application or to test the interaction between multiple kernels.
Verifying the HLS kernel with C simulation and C/RTL co-simulation are block-level tasks. Verifying the HLS kernel with hardware emulation is a system integration task. For more information on the HLS simulation and the hardware emulation flows for Versal ACAP, see this link in the Versal ACAP System Integration and Validation Methodology Guide (UG1388).