If timing cannot be met with the predefined strategies, you can manually explore a custom combination of directives. Because placement typically has a large impact on overall design performance, it can be beneficial to try various placer directives with only the I/O location constraints and with no other placement constraints. By reviewing both WNS and TNS of each placer run (these values can be found in the placer log), you can select two or three directives that provide the best timing results as a basis for the downstream implementation flow.
-helpoption (for example,
place_design -help). For information on strategies, see this link in the Vivado Design Suite User Guide: Implementation (UG904).
For each of these checkpoints, several directives for
route_design can be tried and again only the runs with the best estimated
or final WNS/TNS should be kept. In Non-Project Mode, you must explicitly describe the
flow with a Tcl script and save the best checkpoints. In Project Mode, you can create
individual implementation runs for each placer directive, and launch the runs up to the
placement step. You would continue implementation for the runs that have the best
results after the placer step (as determined by the Tcl-post script).
Physical constraints (Pblocks and DSP and RAM macro constraints) can prevent the placer from finding the most optimal solution. Xilinx therefore recommends that you run the placer directives without any Pblock constraints. The following Tcl command can be used to delete any Pblocks before placement with directives commences:
delete_pblock [get_pblocks *]
<directive> and analyzing placement of the best results can also
provide a template for floorplanning the design or reusing the placement of block RAM
macros or DSP macros, which can stabilize the flow from run to run.