The Xilinx SmartLynq+ module is a High-Speed Debug and Trace module that primarily supports Versal devices. You can use SmartLynq+ modules in your Versal ACAP designs to take advantage of High-Speed Debug Port (HSDP) for reduced configuration times and high-speed debugging connectivity. The SmartLynq+ module can also be used in many cases as a direct replacement for remote lab PC as it includes connectivity via Gigabit Ethernet for a direct connection to your local area network.
To use HSDP with SmartLynq+, the design typically has the HSDP interface enabled in the Control, Interface, and Processing (CIPS) IP along with JTAG over the USB connectivity at the board level to a USB-C connector to interface with the SmartLynq+.
For more information, see this link in the SmartLynq+ Module User Guide (UG1514).