Optimizing Regular Fabric Paths - 2021.1 English

Versal ACAP System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2021-07-26
Version
2021.1 English

Regular fabric paths are paths between fabric registers or shift registers that traverse a mix of resources, such as LUTs. The report_design_analysis Timing Path Characteristics table provides the best logic path topology summary, where the following issues can be identified:

  • Several small LUTs are cascaded

    Mapping to LUTs is impacted by hierarchy, the presence of KEEP_HIERARCHY, DONT_TOUCH, or MARK_DEBUG attributes, or intermediate signals with some fanout (10 and higher). Run the opt_design -remap option or use the AddRemap or ExploreWithRemap directives to collapse smaller LUTs and reduce the number of logic levels. If opt_design is unable to optimize the longest paths due to a net fanout greater than one between the small LUTs, you can force the optimization by setting the LUT_REMAP property on the LUTs.

  • Path ends at shift register (SRL)

    Pull the first register out of the shift register by using the SRL_STYLE attribute in RTL. For details, see this link in the Vivado Design Suite User Guide: Synthesis (UG901). Alternatively, you can use the SRL_STAGES_TO_REG_INPUT property applied prior to opt_design to implement the same optimization. For details, see this link in the Vivado Design Suite User Guide: Implementation (UG904).

    Note: This optimization technique is automatically applied by the report_qor_suggestions Tcl command.
  • Path ends at a fabric register (FD) clock enable or synchronous set/reset

    If the path ending at the data pin (D) has more margin and fewer logic levels, use the EXTRACT_ENABLE or EXTRACT_RESET attribute and set it to "no" on the signal in RTL. Alternatively, you can instruct opt_design to perform the same optimization by setting the CONTROL_SET_REMAP property on the registers to optimize.

    Note: This optimization technique is automatically applied by the report_qor_suggestions Tcl command.
    Tip: To cross-probe from a post-synthesis path to the corresponding RTL view and source code, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
    Note: For more information, see this link in the Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387).