Block Design Type Kernel Project - 2021.1 English

The block design type kernel delivers an IP integrator block design (.bd) at the top-level of the example project. A MicroBlaze processor subsystem is used to sample the control registers and to control the flow of the kernel. The MicroBlaze processor system uses a block RAM as an exchange memory between the host and the kernel instead of a register file.

For each AXI interface, a DMA and math operation sub-blocks are created to provide an example of how to control the kernel execution. The example uses the MicroBlaze AXI4-Stream interfaces to control the AXI Data Mover IP to create an example identical to the one in the RTL kernel type. Also, included is a Vitis IDE project to compile and link an ELF file for the MicroBlaze core. This ELF file is loaded into the Vivado kernel project and initialized directly into the MicroBlaze instruction memory.

The following steps can be used to modify the MicroBlaze processor program:

1. If the design has been updated, you might need to run the Export Hardware option. The option can be found in the File > Export > Export Hardware menu location. When the Export Hardware dialog opens, click OK.
2. The core development kit application can now be invoked. Select Tools > Launch Vitis from the main menu.
3. When the Vitis IDE opens, click X just to the right of the text on the Welcome tab to close the welcome dialog box. This shows an already loaded Vitis IDE project underneath.
4. From the Project Explorer, the source files are under the <Kernel Name>_control/src section. Modify these as appropriate.
5. When updates are complete, compile the source by selecting the menu option Project > Build All > Check for errors/warnings and resolve if necessary. The ELF file is automatically updated in the IDE.
6. Run simulation to test the updated program and debug if necessary.