Design Recommendations for RTL Kernels - 2021.1 English

While the RTL Kernel Wizard assists in packaging RTL designs for use within the Vitis core development kit, the underlying RTL kernels should be designed with recommendations from the UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949).

In addition to adhering to the interface and packaging requirements, the kernels should be designed with the following performance goals in mind:

• Memory Performance Optimizations for AXI4 Interface
• Quality of Results Considerations
• Debug and Verification Considerations