Hardware emulation runs an RTL simulation of the programmable logic design, where the PL kernels are integrated with a cycle-approximate model of the hardware platform.
Hardware emulation is especially useful for the following tasks:
- Checking the functional correctness of the RTL code synthesized from the C, C++, or OpenCL kernel code
- Testing the interactions between different kernels or multiple CUs
- Using hardware waveforms to gain detailed visibility into internal activity of the kernels
- Getting initial performance estimates for the application
Each kernel is compiled to a hardware model (RTL). During hardware emulation, kernels are run in the Vivado logic simulator, with a waveform viewer to examine the kernel design. Some third-party simulators are also supported as described in Simulator Support. In addition, hardware emulation provides performance and resource estimates for the hardware implementation.
SystemC models are provided for the key IP used in the hardware platform, like Versal NoC/DDR memory, CIPS, PS block, AI Engine, UltraScale+ MIG DDR memory, and AXI4 SmartConnect. These IP models are used during hardware emulation to improve simulation performance and results.
In hardware emulation, compile and execution times are longer than software emulation, but it provides a detailed, cycle-accurate, view of kernel activity. Xilinx recommends using small data sets for validation during hardware emulation to keep runtimes manageable.
As discussed in Vitis Compiler Command, the
hardware emulation target is specified in the v++ command with
the -t option:
v++ -t hw_emu ...