Process Execution Modes - 2021.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
Release Date
2022-03-29
Version
2021.1 English

As discussed in Kernel Properties, XRT-managed kernels have two types of execution modes. These modes are determined by block protocols assigned to the kernels by Vitis HLS during kernel compilation. The block protocol can be specified using #pragma HLS INTERFACE. The modes and block protocol to enable them are listed below:

Pipeline
Enabled by the default block protocol of ap_ctrl_chain lets kernels overlap in execution with a single kernel finishing the execution of one task while starting the execution of the next
Sequential
Serial access mode enabled by ap_ctrl_hs requires a kernel to complete the execution of one task before starting the next

For more information on how XRT supports these execution modes, refer to Supported Kernel Execution Models.

Pipeline Execution

If a kernel can accept more data while it is still operating on data from previous transactions, XRT can send the next batch of data as described in Temporal Data Parallelism: Host-to-Kernel Dataflow. Pipeline mode lets the kernel overlap multiple kernel runs, which improves the overall throughput.

To support pipeline mode the kernel has to use the ap_ctrl_chain protocol which is the default protocol used by Vitis HLS. This protocol can also be enabled by assigning the #pragma HLS INTERFACE to the function return as shown in the following example.

void kernel_name( int *inputs,
                  ...         )// Other input or Output ports
{
#pragma HLS INTERFACE ap_ctrl_chain port=return bundle=control

For pipeline execution to be successful, the kernel should have a longer latency for the queue of the kernel, or else there might be insufficient time for the kernel to process each batch of data, and you would not see the benefit of the pipeline. If a pipelined kernel is unable to process data in a pipelined manner, it reverts to sequential execution.

Important: To take advantage of the host-to-kernel dataflow, the kernel must also be written to process data in stages, such as pipelined at the loop-level, as discussed in Loop Pipelining, or pipelined at the task-level, as discussed in Dataflow Optimization.

For legacy reasons, XRT-managed kernels also support pure sequential mode that can be configured using the ap_ctrl_hs block protocol for the function return in the #pragma HLS INTERFACE.

Never-Ending Mode

By default Vitis HLS generates a kernel with synchronization controlled by the host application. The host controls and monitors the start and end of the kernel. However, in some cases the kernel does not need to be controlled by the host, such as in a continuous data stream. These kernels can use an auto_restart signal of the ap_ctrl_chain block protocol, as described in Streaming Data in User-Managed Never-Ending Kernels. This is considered a user-manage kernel because the user sets the ap_start bit and auto_restart bit to start kernel execution, but it is largely a non-software controlled kernel beyond its initial start.