In the Vitis application acceleration development flow, RTL IP from the Vivado® Design Suite can be packaged as XO files that can be linked into an FPGA executable (.xclbin), as long as they adhere to Vivado IP Packaging guidelines, and requirements of the Vitis compiler for linking the system.
As explained in Kernel Properties, RTL
kernels can be user-managed kernels that do not adhere to XRT requirements for execution
control, but rather implement any number of possible control schemes specified by existing RTL
designs. Alternatively, RTL kernels can adhere to the requirements of the
ap_ctrl_chain or ap_ctrl_hs control protocols needed for
XRT-managed kernels.
The following sections describe the kernel interface requirements for the Vitis compiler to link kernels into a system. These requirements are common to software controllable and non-software controlled kernels. The control requirements for XRT-managed kernels are also described, as well as any additional requirements. Finally, the development flow is described to help you package RTL IP in the Vivado® Design Suite as RTL kernels for use in the Vitis environment.