config_interface - 2021.1 English

Description

Specifies the default interface options used to implement the RTL ports of each function during interface synthesis.

Syntax

config_interface [OPTIONS]

Options

-clock_enable[=true|false]

Adds a clock-enable port (ap_ce) to the design. The default is false.

The clock enable prevents all clock operations when it is active-Low. It disables all sequential operations

-default_slave_interface [none | s_axilite]

Enables the default for the slave interface as either none, which is the default for the Vivado IP flow, or as s_axilite which is the default for the Vitis Kernel flow, as described in Vitis HLS Process Overview.

-m_axi_addr64[=true|false]

Globally enables 64-bit addressing for all m_axi ports in the design. By default, this is enabled for the Vitis flow, and otherwise disabled.

-m_axi_alignment_byte_size <size>

Specifies the memory alignment boundary for m_axi interfaces provided as bitwidth in power of two. This can help automatic burst widening. The default value is 64 when open_solution -flow_target vitis, and 0 when the target=vivado. A 0 will allow unaligned interface sizes.

Important: Burst behavior will be incorrect if pointers are not aligned at runtime.

-m_axi_auto_max_ports[=true|false]

If the option is true, all the m_axi interfaces that are not explicitly bundled, with INTERFACE pragmas or directives, will be mapped into individual interfaces, thus increasing the resource utilization (multiple adapters). The default is false and m_axi ports are bundled into a single interface.

-m_axi_buffer_impl [auto | lutram | uram | bram]

Select the implementation for all m_axi internal buffers.

auto

Let the tool choose the implementation.

lutram

Specifies distributed RAM for the buffers.

bram

Use the Block RAM. This is the default setting.

uram

Use the UltraRAM.

-m_axi_conservative_mode

This mode tells the m_axi not to issue a write request until the associated write data is entirely available (typically, buffered into the adapter or already emitted). This can slightly increase write latency but can resolve deadlock due to concurrent requests (read or write) on the memory subsystem. The default is false, and is enabled when the option is specified.

-m_axi_flush_mode

Configure the m_axi adapter to be flushable, writing or reading garbage data if a burst is interrupted due to pipeline blocking, missing data inputs when not in conservative mode, or missing output space. The default is false. This is enabled when the option is specified.

-m_axi_latency <latency>

Globally specifies the expected latency of the m_axi interface, allowing the design to initiate a bus request a number of cycles (latency) before the read or write is expected. The default value is 64 when open_solution -flow_target vitis, and 0 when -flow_target vivado.

-m_axi_max_bitwidth <size>

Specifies the maximum bitwidth for the m_axi interfaces data channel. The default is 1024 bits. The specified value must be a power-of-two, between 8 and 1024. Note that this decreases throughput if the actual accesses are bigger than the required interface, as they will be split into a multi-cycle burst of accesses.

-m_axi_max_read_burst_length <size>

Specifies a global maximum number of data values read during a burst transfer for all m_axi interfaces. The default is 16.

-m_axi_max_widen_bitwidth <size>

Automatic port width resizing to widen bursts for the m_axi interface, up to the chosen bitwidth. The specified value must be a power of 2 between 8 and 1024, and must align with the -m_axi_alignment_size. The default value is 512 when open_solution -flow_target vitis, and 0 when the -flow_target vivado.

-m_axi_max_write_burst_length <size>

Specifies a global maximum number of data values written during a burst transfer for all m_axi interfaces. The default is 16.

-m_axi_min_bitwidth <size>

Specifies the minimum bitwidth for the m_axi interfaces data channel. The default is 8 bits. The value must be a power of 2, between 8 and 1024. Note that this does not necessarily increase throughput if the actual accesses are smaller than the required interface.

-m_axi_num_read_outstanding <size>

Specifies how many read requests can be made to the m_axi interface without a response, before the design stalls. The default value is 16. This implies internal storage in the design, and a FIFO of size:

num_read_outstanding*max_read_burst_length*word_size

-m_axi_num_write_outstanding <size>

Specifies how many write requests can be made to the m_axi interface without a response, before the design stalls. The default value is 16. This implies internal storage in the design, and a FIFO of size:

num_write_outstanding*max_write_burst_length*word_size

-m_axi_offset [off | direct | slave]

Globally controls the offset ports for all m_axi interfaces in the design.

off

No offset port is generated. This is the default value in the Vivado IP flow.

direct

Generates a scalar input offset port for directly passing the address offset into the IP through the offset port.

slave

Generates an offset port and automatically maps it to an AXI4-Lite slave. This is the default value.

-register_io [off | scalar_in | scalar_out | scalar_all]

Globally enables registers for all inputs, all outputs, or all ports on the top function. The default is off.

-s_axilite_data64[=true|false]

Set the data width for the s_axilite interface to 64 bits.

-s_axilite_status_regs [ecc | off]

Enables exposure of ECC error bits in the s_axilite register map via two clear-on-read (COR) counters per BRAM or URAM with ECC enabled.

off

No status registers generated. This is the default setting.

ecc

Enable counters for ECC errors for BRAMs and URAMs

Examples

• Exposes global variables as I/O ports.
• Adds a clock enable port.

config_interface -expose_global -clock_enable