AI Engine Blocksets - 2021.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2021-06-16
Version
2021.1 English
Table 1. AI Engine
Block Description
AIE to HDL Connect the input port of an HDL block with the output port of an AI Engine kernel or AI Engine graph block using an AXI4-Stream interface.
HDL to AIE Connect the output ports of HDL blocks to the input ports of AI Engine blocks using the AXI4-Stream protocol.
AIE to HLS Connect an input port of an HLS kernel block to the output port of an AI Engine block in cases where the data type or complexity of the ports involved do not match.
HLS to AIE Connect an input port of an AI Engine Kernel or AI Engine Graph block to an output port of an HLS Kernel block in cases where the datatype or complexities of the ports involved does not match.
AIE Signal Spec Specify various properties on signals within, as well as at the boundary of an AI Engine subsystem.
To Fixed Size Takes a variable size vector as an input and produces a fixed size vector as output.
Variable Size Signal to Workspace Save variable size signal data from your SimulinkĀ® simulation to the MATLABĀ® workspace.
AIE Class Kernel Import class-based AI Engine kernels
AIE Graph Import an AI Engine graph.
AIE Kernel Import an AI Engine kernel.
HLS Kernel Import an HLS kernel code with a streaming interface.
FIR Asymmetric Decimation Implements the FIR Asymmetric Decimation filter targeted for AI Engines.
FIR Asymmetric Filter Implements the Single Rate Asymmetric FIR Filter targeted for AI Engines.
FIR Fractional Interpolation Implements the FIR Fractional Asymmetric Interpolation filter targeted for AI Engines.
FIR Halfband Decimator Implements the FIR Halfband Decimator targeted for AI Engines.
FIR Halfband Interpolator Implements the FIR Halfband Interpolator targeted for AI Engines.
FIR Interpolation Implements the FIR Asymmetric Interpolation filter targeted for AI Engines.
FIR Symmetric Decimation Implements the FIR Symmetric Decimation Filter targeted for AI Engines.
FIR Symmetric Filter Implements the Single Rate Symmetric FIR Filter targeted for AI Engines.
IFFT Implements the Inverse FFT targeted for AI Engines which use the rounding method and saturates the output samples on overflow.
FFT Implements the FFT targeted for AI Engines which use rounding method and saturates the output samples on overflow.
RTP Source Used as a source for the RTP input of an AI Engine block. When the RTP input is a scalar, the 'RTP Value' parameter should be a row vector. At each time step, the output is set to one of the elements of the vector starting with the first element. If an element of the vector is NaN, at the corresponding sampling time, the output will be an empty variable size signal.
To Variable Size Takes a fixed sized vector input and produces a variable sized vector output. The maximum size of the output vector is specified by the Output Size parameter. If there is not enough samples to pack the output, the output will be an empty variable size signal.