AIE to HDL - 2021.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2021-06-16
Version
2021.1 English

This block is used to connect the input port of an HDL block with the output port of an AI Engine kernel or AI Engine graph block using an AXI4-Stream interface.



Library

AI Engine/Interfaces

Description

This block provides an interface between the AI Engine and HDL blocks.
  • Input to the AIE to HDL block is a variable size signal (data) from AI Engine blocks along with the tready signal which indicates that the consumer can accept a transfer.
  • Output from the AIE to HDL block is tdata and tvalid that indicates the producer has valid data available. A transfer takes place when both tvalid and tready are asserted.

Parameters

Output Data Type
The following table shows different Output data types that are supported by AIE to HDL blocks and the corresponding input data type to the block.
Output Data Type Input to AIE - HDL Block
int32 int32
uint32 int8, uint8, int16, uint16, uint32, float, cint16
sfix64 x_sfix64
ufix64 int8, uint8, int16, uint16, cint16, int32, uint32, cint32, x_ufix64, float, float(c)
ufix128 int8, uint8, int16, uint16, cint16, int32, uint32, cint32, x_sfix64, x_ufix64, float, float(c)
Output Sample Time
This parameter depends on the input size to the block and the initiation interval of the HDL design (the number of cycles before the HDL design can consume the next sample).
Note: Refer to AI Engine Library and product examples for more information.