Example: Setting Block Parameters - 2021.1 English

Consider the following example to understand how to set the block parameters for AIE to HDL and HDL to AIE blocks.

Figure 1. Example: Setting Block Parameters

You can observe one HDL block, connected between two AI Engine kernel blocks using AIE-HDL and HDL-AIE blocks as gateways between two domains. The Input to the AIE_kernel_1 block is a vector of size 128 and the output is a variable size signal of maximum depth 256 and the AIE to HDL block accepts the variable size signal as input. The Input Sample time is 0.5.

As per the RTL design, it takes the HDL block 19 clock cycles before it can process the next set of input data. This is called the initiation interval or II for short. Because the simulation of the HDL blocks are cycle-accurate, the output of the AIE to HDL block should be at least 19 times faster than its input or a buffer overflow situation may occur. The following figure show the settings for the block.

Figure 2. AIE to HDL Parameters

Here, the Output Data type parameter can be set to any supported type as mentioned in AIE to HDL. For this example, it is set to uint32, because the succeeding HDL block accepts uint32. The Output Sample time should be at least equal to the Input Sample time over 'Initiation interval(II) of Model Composer HDL design'. This is required to avoid buffer overflow.

Output Sample time = Input Sample time/Initiation Interval of Model Composer HDL design.

For this example, the Input Sample time = 0.5 and Initiation Interval = 20. So, the output sample time is '0.5/20'.

The block parameters of HDL- AIE block should be given as follows.

Figure 3. HDL to AIE Parameters

The Output Data Type parameter should be the same as the the input of the succeeding AI Engine block. The output of this block is a variable size signal. In this example, it is complex integer of type int16.

The Output Sample Time parameter is correlated with the Samples per output frame and should be set based on the input sample rate. This is required to make the sample rate to and from the AI Engine domains have the same rate. In this example, the Output Sample time should be 0.5 with Samples per output frame as 256. If the HDL block produces more samples per frame, say 512, the Output Sample time should be adjusted to 0.25 so that the sample rate matches with the input to the AIE to HDL block.

The Tready Sample Time value should be given the same value as the Output Sample Time of the AIE-HDL block.