Generating Model Composer HDL IP - 2021.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2021-06-16
Version
2021.1 English

Model Composer can automatically generate an RTL which can be imported and used along side other blocks in the HDL library. When Model Composer generates HDL output, it first writes the C++ code as described in Generating C++ Code, and then it synthesizes RTL code from the C++ code. This process begins when you set the Target in the Model Composer Hub block to System Generator. This command creates an IP package for HDL library.

Model Composer displays a transcript window of the process. When the process has concluded, the MATLAB window displays the Synthesis Report for your review, as shown in the figure below. The Synthesis Report includes details on the estimated performance and resource utilization of the RTL design synthesized by Model Composer. You can review this report to see the estimates and review your model.

Figure 1. Synthesis Report

When Model Composer has completed synthesizing the RTL, it reports the message Exporting RTL as an IP for System Generator for DSP to the transcript window. This process is handled by a Tcl script, run_hls.tcl, that Model Composer writes to export the HDL IP.

Model Composer generates the following outputs from the algorithm:
  • SystemC (IEEE 1666-2006, version 2.2)
  • VHDL (IEEE 1076-2000)
  • Verilog (IEEE 1364-2001)
  • Report files created during synthesis, C/RTL co-simulation, and IP packaging.

When Model Composer has generated the HDL IP, you can find it in the project directory structure as shown in the following figure. The Edge_Detection_Sysgen folder is the Code Directory specified by the Model Composer Hub. The Edge_Detection_prj folder is a project created by the run_hls.tcl script. The solution1 folder is a Vitis HLS solution. For more information refer to the Vitis High-Level Synthesis User Guide (UG1399). The Solution1.json file contains the information needed to use the subsystem IP in Model Composer HDL design..

Figure 2. System Generator Output
You can import a Model Composer generated HDL IP into a Model Composer HDL model using the following steps:
  1. From within an open Model Compose HDL model, right-click in the canvas of the Simulink Editor and select the Xilinx BlockAdd command. This opens a menu of HDL Library blocks that can be added to your model.
  2. Scroll down the list in dialog box, or type "HLS" in the Add Block search field to locate the Vitis HLS block and add it to your model.
  3. Double-click on the newly added block to open the Vitis HLS Block Parameter dialog box as shown below.
    Figure 3. Vitis HLS Block
  4. Browse to the solution directory of the Vitis HLS project where the Model Composer output was generated. In the example above, browse to the Lucas_Kanade_prj/solution1 folder and select OK.

The Vitis HLS template block is converted to the Edge Detection IP in the Model Composer HDL model. You may need to drag the corners of the IP block to expand it as needed for your model. The block is initially sized to match the Vitis HLS template. The following figure shows the HDL IP generated from the Model Composer HLS model.

Figure 4. Vitis HLS Block

If any of the function arguments on the Model Composer subsystem module are transformed by Vitis HLS into a composite port, the signal type information for that port cannot be determined and included in the HDL IP block. Any design that uses the reshape, mapping, or data packing optimization on ports must have the port type information manually specified in Model Composer HDL model for these composite ports. You should know how the composite ports were originally created and then use slice and reinterpretation blocks in the HDL model to connect the Vitis HLS block to other blocks in the system.

For example, if three 8-bit in-out ports R, G and B are packed into a 24-bit input port (RGB_in) and a 24-bit output port (RGB_out) ports. After the IP block has been included in Model Composer HDL:
  • The 24-bit input port (RGB_in) would need to be driven by an HDL block that correctly groups three 8-bit input signals (R_in, G_in and B_in) into a 24-bit input bus.
  • The 24-bit output bus (RGB_out) would need to be correctly split into three 8-bit signals (R_out, G_out, and B_out).
Tip: See the HDL Library documentation for details on using the slice and reinterpretation blocks to connect to composite type ports.