Review the Results - 2021.1 English

Vitis Model Composer Tutorial: (UG1498)

Document ID
UG1498
Release Date
2021-07-16
Version
2021.1 English
The output from design compilation process is written to the netlist directory. This directory contains three subdirectories:
sysgen
This contains the RTL design description written in the industry standard VHDL format. This is provided for users experienced in hardware design who wish to view the detailed results.
ip
This directory contains the design IP, captured in Xilinx IP catalog format, which is used to transfer the design into the Xilinx Vivado. Lab 5: Using AXI Interfaces and IP Integrator, presented later in this document, explains in detail how to transfer your design IP into the Vivado for implementation in an FPGA
ip_catalog
This directory contains an example Vivado project with the design IP already included. This project is provided only as a means of quick analysis.

The previous Resource Analyzer: Lab1_1 figure shows the summary of resources used after the design is synthesized. You can also review the results in hardware by using the example Vivado project in the ip_catalog directory.

Important: The Vivado project provided in the ip_catalog directory does not contain top-level I/O buffers. The results of synthesis provide a very good estimate of the final design results; however, the results from this project cannot be used to create the final FPGA.

When you have reviewed the results, exit the Lab1_1.slx Simulink worksheet.