After the application mapping is complete, you can move to the dataflow modeling phase. The memory requirements of the design can be modeled using the AXI NoC IP in the Vivado® IP integrator. The AXI NoC IP supports the AXI memory-mapped protocol. Each instance of the AXI NoC IP specifies a set of connections to be mapped onto the physical NoC, along with the QoS requirements for each connection. A design can have any number of instances of the NoC IP. The Vivado tools automatically aggregate the connectivity and QoS information from all of the logical NoC instances to form a unified traffic specification.
In early phases, you can use traffic generators to simulate the dataflow of a real application. The traffic generator reads and writes from DDR memory through an AXI NoC instance. You can include the AXI performance monitors, which can be used to report the average bandwidth and latency achieved by each of the AXI connections. The Vivado IP integrator offers designer assistance for including traffic generators in your design.
For Versal ACAPs, the Vivado tools include a NoC compiler that uses the unified traffic specification as input. Validating the design in the Vivado IP integrator invokes the NoC compiler, which creates a formalized traffic specification with entry and exit points of the NoC. At this point, the design has been elaborated and the netlist simulation model exported.
In this dataflow modeling phase, you can keep iterating over the application mapping to maximize the QoS from the NoC and DDRMC. The Validate Design step in the Vivado IP integrator also alerts you if the QoS settings cannot be met. For more information, see the Vivado Design Tutorials: Versal NoC DDRMC.