The dataflow simulation phase allows you to perform dynamic analysis of your traffic patterns through the NoC and DDR memory. The Vivado tools support either RTL (including SystemVerilog) or SystemC models for performance-based or functional simulation. In the Vivado IP integrator, you can select between these simulation models. The Vivado simulator includes a transaction view feature that provides a higher level waveform view of AXI bus transactions. For more information, see this link and this link in the Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).