One of the key considerations in a hardware-only system design is the dataflow in the design. Typically these designs have the following components:
- Multiple high-speed I/O interfaces
- Internal data buffering and storage with a memory hierarchy comprised of on-chip RAM and external DDR memory
- Internal data-processing logic
It is important to create a DDRMC-NoC configuration for the design that is capable of handling the external and internal traffic bandwidth and latency requirements. Xilinx recommends conducting traffic analysis to evaluate and finalize the traffic flow before proceeding to the overall integration and implementation phase of the design.
The key distinction between the hardware-only systems and the embedded systems is that hardware-only systems do not rely on an embedded or external processor. Instead, hardware-only systems use the PMC as the primary way to program and control the implemented hardware design. In most cases, Versal ACAP hardware-only system designs follow UltraScale+™ device design methodology with the exception of the hard IP implemented on Versal devices, specifically DDRMC, NoC, and hardened controllers (such as PCIe® interfaces and MRMAC IP).