The complexity of Versal™ ACAP with its different compute domains challenges traditional FPGA simulation methods. With traditional FPGA simulation, most of the design can be verified using logic simulation. With Versal ACAP, the programmable logic is only one of the compute domains, and the simulation methodology must consider the software domain as well as the AI Engine domain when used.
The system simulation methodology for Versal ACAP is based on a hierarchical approach. This methodology acknowledges the need to simulate each compute domain independently, while also being able to simulate the entire system when appropriate.
The system simulation methodology is built around the following key concepts:
- Scope of the simulation
- The simulation can include the entire system or just portions of the system. Xilinx recommends testing blocks and functions individually before integrating and simulating them in the entire system. You can use different simulation flows to test the different compute domains, including the PS, PL, and AI Engine.
- Abstraction of the simulation
- In some cases, you can simulate specific functions at different abstraction levels. For example, you can simulate AI Engine code either as untimed or cycle-approximate models. You can simulate HLS code either as untimed or cycle-accurate RTL models. You can simulate specific Versal ACAP infrastructure blocks, such as the NoC or DDR memory controllers, as SystemC transaction-level models (TLM) or as RTL models. Abstraction allows you to trade simulation speed for simulation accuracy.
- Purpose of the simulation
- The purpose of each simulation can vary. For example, is the focus on functional validation or performance measurement? Is the intention to test a single function or the interactions between multiple functions? Different simulation purposes rely on different simulation setups and configurations. Purpose is closely related to scope and abstraction.