Versal ACAP Board System Design Methodology Guide (UG1506) - 2021.1 English

Document ID: UG1506
ft:locale: English (United States)
Release Date: 2021-08-04
Version: 2021.1 English

Revision History
Introduction
About the Versal ACAP Design Methodology
Navigating Content by Design Process
About This Guide
PCB Layout Recommendations
Aligning with Physical Components on the PCB
Power Distribution System
Thermal Solution Considerations
PCB Design Considerations
Device Power Aspects and System Dependencies
Power Supply Paths on Devices
Power Types
Power-On
Startup Power
Static Power
Dynamic Power
Factors Impacting Power
Environmental Factors Impacting Power
Power Rail Consolidation Impacting Power
Power Models Accuracy
Device Power and the Overall System Design Process
Worst Case Power Analysis Using Xilinx Power Estimator (XPE)
NoC and DDRMC Power Estimation
AI Engine Power Estimation
Clock Resource Planning and Assignment
I/O Planning Design Flows
Types of Vivado Design Suite Projects for I/O Planning
Pre-RTL I/O Planning
Netlist-Based I/O Planning
Required Information for Pin Assignment
Pinout Selection
General Pinout Selection Guidelines
Platform Management Controller Pins
Memory and Advanced I/O Interfaces
Gigabit Transceivers (GTs)
Interface Bandwidth Validation
Boot and Configuration
Board Design Tips
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Please Read: Important Legal Notices

Back to home page